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3 ghz hdmi 2 :2 crosspoint transceiver with on - screen display data sheet adv7626 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third pa rties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respe ctive owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 2 - input, 2 - output cross point hdmi transceiver hdmi support 3 ghz video support ( up to 4k 2k) audio return channel (arc) 3d tv support content type bits cec 1.4 - compatible extended colorimetry character - and icon - based on - screen display (osd) 3d osd overlay on all mandatory 3d formats support for osd overlay on 3 ghz video formats high - b andwidth digital content protection (hdcp 1.4) hdcp repeater support : u p to 127 ksvs supported 300 mhz maximum tmds clock frequency (up to 4k 2k) 48- / 36 - / 30- bit d eep c olor input modes supported ultralow jitter digital pll (100% deskew) 2 independent hdmi receiver s 3 ghz support on all inputs adaptive equalizer for cable lengths up to 30 meters flexible internal edid ram supports dual edids replication of either du al edid on any input port 5 v detect inputs hot p lug assert control outputs 2 independent hdmi transmitters 3 ghz support on all outputs edid data extraction hot p lug detect (hpd) input s audio return channel (arc) receiver per transmitter 3 ghz c olor sp ace converter (csc) per transmitter audio hdmi - compatible audio interface 2 independent 8 - channel audio extraction ports 2 independent 8 - channel audio insertion ports s/pdif (iec 60958 - compatible) digital audio input/output super a udio cd ? (sacd) with dsd input/output interface high bit rate (hbr) audio dolby? truehd dts - hd master audio? full audio input and output support general interrupt controller s tandard identification (stdi) circuit software libraries, driver , and application available applications a vr sound bar with hdmi repeater support matrix switch other repeater applications functional block dia gram 1 1832-001 hdmi_rx_a tmds hdmi txs cp-lites osd rx edid with replic a t or tx edid/hdcp controller interrupts spi i 2 c 2:2 crosspoint mux digi t a l audio input ports digi t a l audio output ports hdmi_tx_a hdmi_tx_b cec a cec b hdmi_rx_b ddc tmds hdcp arc ddc tmds hdcp arc ddc tmds ddc adv7626 h d m i r x s h d c p h d c p figure 1.
adv7626 data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 detailed functional block diagram .............................................. 4 specifications ..................................................................................... 5 digital, hdmi, and ac specifications ...................................... 5 data and i 2 c timing characteristics ......................................... 6 power specifications .................................................................. 12 absolute maximum ratings .......................................................... 14 package thermal performance ................................................. 14 esd caution ................................................................................ 14 pin configuration and function descriptions ........................... 15 power supply recommendations ................................................. 21 power - up sequence ................................................................... 21 power - down sequence .............................................................. 21 theory of operation ...................................................................... 22 hdmi receiver ........................................................................... 22 hdcp repeater functionality ................................................. 22 digital audio ports .................................................................... 22 on - screen display ..................................................................... 22 hdmi transmitters ................................................................... 22 i 2 c interface ................................................................................ 22 other features ............................................................................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 1 2 /13 rev ision 0: initial version
dat a sheet adv7626 rev. 0 | page 3 of 24 general description the adv7626 is a high performance, high - definition multi - media interface (hdmi ? ) transceiver with c ross point and splitter capabilities. t he adv7626 supports 3 ghz video and features two independent hdmi receivers, two independent hdmi trans - mitters, two audio output ports, and two audio input ports. the adv7626 supports all hdcp repeater functions through fully tested analog devices, inc., repeater software libraries and drivers. the hdmi receivers and transmitters in the adv7626 support the reception and transmission of 3 ghz video formats up to 4k 2k at 24 hz/25 hz/30 hz, in addition to all mandatory hdmi 3d tv formats. the receivers and transmitters also provide support for thx? media director?. each hdmi receiver features an integrated equalizer that ensures robust operation of the interface with cable lengths up to 30 meters. the hdmi receivers share a 768 - byte volatile extended display identification data ( edid ) memory , which can facilitate one or two edids , one for each receiver . each hdmi port features dedicated 5 v d etect and h ot p lug ? assert pins. each hdmi transmitter supports audio return channel (arc) and features an integrated hdmi cec controller that supports c apability discovery and control (cdc). the adv7626 offers two dedicated audio output ports and two dedicated audio input ports. each audio port supports the extrac - tion and insertion of up to eig ht channels of audio data out of or into the hdmi streams. hdmi audio formats, including i 2 s, s/pdif, direct stream digital (dsd) , and high bit rate (hbr) audio are supported. the adv7626 has an integrated on - screen display (osd) generator that enable s the creation and control of high quality character - and icon - based system status and control displays. th e osd can be overlaid on 3 ghz video formats and 3d video. customers who are interested in u sing osd are provided with blimp, the analog devices osd development tool. the adv7626 is provided in a space - saving, 260 - ball , 15 mm 15 mm csp_ bga surface - mount, rohs - compliant package and is specified over the 0c to 70c temperature range.
adv7626 data sheet rev. 0 | page 4 of 24 detailed functional block dia gram 1 1832-002 hdmi rx1 hdmi rx2 rx2 audio extraction interrupt controller int1 ep_cs spi hdc p keys memo r y tx hpd/arc plls 5v detect hp a contro l ddc contro l rx1 audio extraction cec_ a cec master a cec master b cec_b tx edid/hdc p controller txa_hpd_arc? osd blend a osd blend b osd hdmi tx a tx a audio insertion txb audio insertion cp-lite a 4:2:2 t o 4:4:4 xt al+ i 2 c controller scl clock gener a tion tx a pl l txb pl l cp-lite b 4:2:2 t o 4:4:4 digi t al audio output port 1 ap1_out0 ap1_out5 digi t al audio output port 2 digi t al audio input port 1 ap2_out0 ap2_out5 digi t al audio input port 2 ap1_in0 ap2_in0 ap1_in5 ap2_in5 ddc_scl_tx a ddc_sda_tx a ddc_scl_txb ddc_sda_txb txa_0 txa_1 txa_2 txa_c txb_c txb_0 txb_1 txb_2 xt al? rxa_h p a rxa_hpb rxa_5v rxb_5v rxa_0 rxa_1 rxa_2 rxb_0 rxb_1 rxb_2 rxa_c rxb_c ddc_scl_rx a ddc_sda_rx a ddc_scl_rxb ddc_sda_rxb sda alsb cs ap1_out_sclk ap1_out_mclk txa_arc+ txb_hpd_arc? txb_arc+ ap1_in_sclk ap1_in_mclk ap2_in_sclk ap2_in_mclk arc_ a arc_b csc dcm hdc p hdmi txb csc dcm hdc p hdc p hdc p sampler equalizer sampler equalizer ap2_out_sclk ap2_out_mclk ep_sclk ep_miso ep_mosi int2 figure 2. detailed functional block diagram
dat a sheet adv7626 rev. 0 | page 5 of 24 specifications av dd_t x a = 1.8 v 5%, avdd_txb = 1.8 v 5%, cvdd = 1.8 v 5%, dvdd = 1.8 v 5% , dvddio = 3.3 v 5%, pvdd = 1.8 v 5%, pvdd_txa = 1.8 v 5%, pvdd_txb = 1.8 v 5%, tvdd = 3.3 v 5%, t min to t max = 0c to 70c. digital, hdmi, and a c specifications table 1 . parameter test conditions/comments min typ max un it digital inputs input high voltage (v ih ) 2 v input low voltage (v il ) 0.8 v input leakage current (i in ) ? 60 +60 a input capacitance (c in ) 20 pf digital inputs (5 v tolerant) 1 input high voltage (v ih ) 2.85 v input low volta ge (v il ) 0.8 v input leakage current (i in ) rxa_5v and rxb_5v inputs ? 450 +450 a all other 5 v tolerant digital inputs ? 60 +60 a digital outputs output high voltage (v oh ) 2.4 v output low voltage (v ol ) 0.4 v high impedance leakage c urrent (i leak ) 10 a output capacitance (c out ) 20 pf digital outputs (5 v tolerant) 2 output high voltage (v oh ) 4.85 v output low voltage (v ol ) 0.4 v ac specifications tmds input clock range 25 300 mhz tmds output clock freque ncy 25 300 mhz 1 the following pins are 5 v tolerant inputs : ddc_scl_rxa , ddc_sda_rxa , ddc_scl_rxb , ddc_sda_rxb , rxa_5v, rxb_5v, cec_a , ddc_scl_txa , ddc_sda_txa , txa_hpd_arc ?, txa_arc+ , cec_b , ddc_scl_txb , ddc_sda_txb , txb_hpd_arc ?, and txb_arc+ . 2 the following pins are 5 v tolerant outputs : rxa_hpa and rx b _hpa .
adv7626 data sheet rev. 0 | page 6 of 24 data and i 2 c timing characteris tics table 2 . parameter symbol test conditions/comments min typ max unit video system clock and xtal crystal nominal frequency 27.0 mhz crystal frequency stability 50 ppm external clock source external crystal must operate at 1.8 v input high voltage v ih xtal driven with external clock source 1.2 v input low voltage v il xtal driven with external clock source 0.4 v serial port ep_sclk fre quency 27 mhz audio sclk frequency 49.152 mhz audio mclk frequency 98.304 mhz audio dsd clock frequency 5.6448 mhz reset feature reset pulse width 5 ms i 2 c ports (fast mode) xcl frequency 1 400 khz xcl minimum pul se width high 1 t 1 600 ns xcl minimum pulse width low 1 t 2 1.3 s start condition hold time t 3 600 ns start condition setup time t 4 600 ns xda setup t ime 2 t 5 100 ns xcl and xda rise time 1 , 2 t 6 300 ns xcl and xda fall time 1 , 2 t 7 300 ns setup time (stop condition) t 8 0.6 s serial port , master mode 3 , 4 spi mode 0 ep_ cs falling edge to ep_sclk rising/falling edge t 9 , t 10 1 ep_sclk periods 1.5 ep_sclk periods ns ep_sclk risi ng/falling edge to ep_ cs rising edge t 11 , t 12 1 ep_sclk periods 1.5 ep_sclk periods ns ep_ cs pulse width 5 t 13 1000 ns ep_sclk high time t 14 40 60 % duty cycle ep_sclk low time 40 60 % duty cyc le ep_mosi start of data invalid to ep_sclk falling edge t 15 0 ns ep_ cs start of data invalid to ep_sclk falling edge t 15 0 ns ep_sclk falling edge to ep_mosi end of data invalid t 16 2.15 ns ep_sclk falling edge to ep_ cs end of data invalid t 16 2.15 ns ep_miso setup time t 17 valid regardless of the ep_sclk active edge used 7.5 ns ep_miso hold time t 18 valid regardless of the ep_sclk active edge used 0 ns serial port, slave mode 3 , 4 spi mode 0 ep_ cs falling edge to ep_sclk rising edge t 20 10 ns final ep_sclk rising edge to ep_ cs rising edge t 22 10 ns ep_ cs pulse width 5 t 23 20 ep_sclk periods ns
dat a sheet adv7626 rev. 0 | page 7 of 24 parameter symbol test conditions/comments min typ max unit ep_sclk high time t 24 45 55 % duty cycle ep_sclk low time 45 55 % duty cycle ep_mosi setup time t 25 0.5 ns ep_mo si hold time t 26 1.4 ns ep_sclk falling edge to ep_miso start of data invalid t 27 5.5 ns ep_sclk falling edge to ep_miso end of data invalid t 28 9 ns audio input ports , i 2 s input apx_in_sclk high time t 37 45 55 % duty cycle apx_in_scl k low time 45 55 % duty cycle apx_in data setup time t 38 2.3 ns apx_in data hold time t 39 1.6 ns audio input ports , dsd input apx_in_sclk high time t 40 45 55 % duty cycle apx_in_sclk low time 45 55 % duty cycle apx_in dsd data set up time t 41 2.3 ns apx_in dsd data hold time t 42 1.6 ns audio output ports , i 2 s output apx_out_sclk high time t 46 45 55 % duty cycle apx_out_sclk low time 45 55 % duty cycle apx_out lrclk transition time t 47 start of invalid lrclk to falling apx_out_sclk edge 10 ns apx_out lrclk transition time t 48 falling apx_out_sclk edge to end of invalid lrclk 10 ns apx_out data transition time t 49 start of invalid data to falling apx_out_sclk edge 10 ns apx_out data transition time t 50 fa lling apx_out_sclk edge to end of invalid data 10 ns audio output ports , dsd output apx_out_sclk high time t 51 45 55 % duty cycle apx_out_sclk low time 45 55 % duty cycle apx_out dsd data transition time t 52 start of invalid data to fallin g apx_out_sclk edge 10 ns apx_out dsd data transition time t 53 falling apx_out_sclk edge to end of invalid data 10 ns 1 xcl refers to scl, ddc_scl_r x a, and ddc_scl_r xb. 2 xda refers to sda, ddc_sda_r x a, and ddc_sda_r x b. 3 spi mode 0 only . 4 all serial port measurements are for cpha = 0, cpol = 0 (clock is low in idle state ; negative edge of clock is used to transmit data and positive edge is used to sample data). 5 measurements guaranteed by design only.
adv7626 data sheet rev. 0 | page 8 of 24 timing diagrams xd a xc l t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 1 1832-003 figure 3. i 2 c timing instruction (0x0b) 24-bit address dumm y byte 7 6 5 4 3 2 1 0 dat a out 2 ep_mosi ep_miso 7 6 5 4 3 2 1 0 dat a out 1 ep_sclk ep_cs t 1 1 t 13 t 12 t 9 t 10 23 22 21 ... 3 2 1 0 7 6 5 4 3 2 1 0 1 1832-004 figure 4 . detailed spi master ti ming diagram (spi mode 0, cpol = cpha = 0) ep_sclk ep_mosi ep_miso ( f alling edge capture) ep_miso (rising edge capture) t 17 t 15 t 16 t 18 t 17 t 18 t 14 ep_cs 1 1832-005 figure 5. spi master mo de timing (spi mode 0) device address subaddress d at a in 0 d at a in 1 dumm y byte d at a out 0 d at a out 0 d at a out 1 w/r 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 t 23 t 22 ep_mosi del a y mode 1 ep_miso del a y mode 0 ep_miso ep_sclk t 20 ep_cs 1 1832-006 figure 6 . detailed spi slave timing diagram (spi mode 0, cpol = cpha = 0)
dat a sheet adv7626 rev. 0 | page 9 of 24 ep_sclk ep_mosi ep_miso t 24 t 25 t 26 t 27 t 28 1 1832-008 figure 7. spi slave mode timing (spi mode 0) t 39 t 38 sclk i2s[3:0] lrclk t 37 s c l k l r c l k i n p u t p o r t audio input ports i 2 s signal assignment i 2 s [ 3 : 0 ] a p 1 _ i n _ s c l k a p 1 _ i n a p 1 _ i n 5 a p 1 _ i n [ 4 : 1 ] a p 2 _ i n _ s c l k a p 2 _ i n a p 2 _ i n 5 a p 2 _ i n [ 4 : 1 ] 1 1832-012 figure 8. i 2 s input timing lrclk left right i 2 s s t andard i 2 s form a t = 00 32 clock slots 32 clock slots msb left msb right sclk i2s[3:0] lsb lsb 1 1832-013 figure 9. i 2 s standard audio , data width 16 to 24 bits per channel left right 16 clock slots 16 clock slots msb left lsb left msb right lsb right lrclk sclk i2s[3:0] lsb 1 1832-014 figure 10 . i 2 s standard audio , 16 - bit samp les only
adv7626 data sheet rev. 0 | page 10 of 24 lrclk sclk i2s[3:0] msb ? 1 msb ? 1 msb msb msb msb msb msb msb msb lsb lsb left right serial audio right justified i 2 s format = 01 msb extended msb extended 32 clock slots 32 clock slots 1 1832-015 figure 11 . serial audio , right - justified lrclk sclk i2s[3:0] msb msb lsb lsb left right 32 clock slots 32 clock slots serial audio left justified i 2 s format = 10 1 1832-016 figure 12 . serial audio , left - justified lrclk sclk i2s[3:0] channe l a channe l b frame n + 1 frame n p c u v p c u msb v msb lsb lsb 32 clock slots 32 clock slots aes3 direct audio i 2 s form a t = 1 1 1 1832-017 figure 13 . aes3 direct audio t 40 t 41 t 42 apx_in_sclk apx_in[5:0] notes 1. apx refers to the audio input ports ap1_in and ap2_in. 1 1832-018 figure 14 . dsd input timi ng
dat a sheet adv7626 rev. 0 | page 11 of 24 apx_out_sclk l r c l k i2 s x l e f t - j u s t if ie d m o d e i2 s x r ig h t - j u s t if ie d m o d e i2 s x i 2 s m o d e m s b m s b ? 1 t 4 7 t 4 6 t 4 9 t 5 0 t 4 8 m s b m s b ? 1 l s b m s b t 4 9 t 5 0 t 4 9 t 5 0 notes 1. apx refers to the audio output ports ap1_out and ap2_out. 2. lrclk is a signa l accessible vi a apx_out5. 3. i2sx are signals accessible vi a apx_out1 t o apx_out4. 1 1832-020 figure 15 . i 2 s output timing t 5 1 t 5 3 t 5 2 apx_out_sclk apx_out[5:0] notes 1. apx refers t o the audio output ports ap1_out and ap2_ou t . 1 1832-021 figure 16 . dsd output timing
adv7626 data sheet rev. 0 | page 12 of 24 power specifications table 3 . parameter symbol min typ max unit power supplies hdmi txa an alog power supply avdd_txa 1.71 1.8 1.89 v hdmi txb analog power supply avdd_txb 1.71 1.8 1.89 v comparator power supply cvdd 1.71 1.8 1.89 v digital power supply dvdd 1.71 1.8 1.89 v digital i/o power supply dvddio 3.14 3.3 3.46 v pll power supply pv dd 1.71 1.8 1.89 v hdmi txa pll power supply pvdd_txa 1.71 1.8 1.89 v hdmi txb pll power supply pvdd_txb 1.71 1.8 1.89 v termination power supply tvdd 3.14 3.3 3.46 v current consumption mux mode 1 , 2 hdmi txa analog power supply i avdd_txa 23.2 ma hdmi txb analog power supply i avdd_txb 23.2 ma comparator power supply i cvdd 196 ma digital core power supply i dvdd 326.1 ma digital i/o power supply i dvddio 0.1 ma pll power supply i pvdd 69.7 ma hdmi txa pll power supply i pvdd_txa 71.5 ma hdmi txb pll power supply i pvdd_txb 71.5 ma termination power supply i tvdd 116 ma current consumption audio extract/ audio insert mode 1 , 3 hdmi txa analog power supply i avdd_txa 26.2 ma hdm i txb analog power supply i avdd_txb 26.2 ma comparator power supply i cvdd 184 ma digital core power supply i dvdd 436.0 ma digital i/o power supply i dvddio 0.05 ma pll power supply i pvdd 64 ma hdmi txa pll power supply i pvdd_txa 71.1 ma hd mi txb pll power supply i pvdd_txb 71.1 ma termination power supply i tvdd 115 ma current consumption splitter mode 1 , 4 hdmi txa analog power supply i avdd_txa 26.2 ma hdmi txb analog power supply i avdd_txb 26.2 ma comparator power supply i cvdd 93 ma digital core power supply i dvdd 243.5 ma digital i/o power supply i dvddio 0.05 ma pll power supply i pvdd 33.5 ma hdmi txa pll power supply i pvdd_txa 71.1 ma hdmi txb pll power supply i p vdd_txb 71.1 ma termination power supply i tvdd 115 ma current consumption power - down mode 0 1 , 5 hdmi txa analog power supply i avdd_txa 0.65 ma hdmi txb analog power supply i avdd_txb 0.65 ma co mparator power supply i cvdd 0.84 ma digital core power supply i dvdd 0.25 ma digital i/o power supply i dvddio 0.21 ma pll power supply i pvdd 0.02 ma hdmi txa pll power supply i pvdd_txa 0.05 ma hdmi txb pll power supply i pvdd_txb 0.05 ma te rmination power supply i tvdd 0.14 ma
dat a sheet adv7626 rev. 0 | page 13 of 24 parameter symbol min typ max unit current consumption power - down mode 1 1 , 6 hdmi txa analog power supply i avdd_txa 0.95 ma hdmi txb analog power supply i avdd_txb 0.95 ma comparator power suppl y i cvdd 0.84 ma digital core power supply i dvdd 0.95 ma digital i/o power supply i dvddio 0.21 ma pll power supply i pvdd 0.02 ma hdmi txa pll power supply i pvdd_txa 0.05 ma hdmi txb pll power supply i pvdd_txb 0.05 ma termination power supp ly i tvdd 0.14 ma current consumption example max imum operating mode 1 , 7 hdmi txa analog power supply i avdd_txa 3 1 .00 ma hdmi txb analog power supply i avdd_txb 31 .00 ma comparator power supply i cv dd 213.00 ma digital core power supply i dvdd 530.00 ma digital i/o power supply i dvddio 0.20 ma pll power supply i pvdd 7 5 .00 ma hdmi txa pll power supply i pvdd_txa 80 .00 ma hdmi txb pll power supply i pvdd_txb 80.00 ma termination power su pply i tvdd 128 .00 ma 1 d ata recorded during lab ch aracteri z ation . typical current consumption values are recorded with nominal voltage supply levels and at room temperature. 2 adv7626 configured in m ux m ode with two active hdmi rx inputs and two hdmi tx outputs in use. 4k 2k at 30 hz video format with pseudo random test pattern applied to each hdmi rx input port. hdmi rx termination closed on the two hdmi rx input ports. hdmi tx source termination enabled. 3 adv7626 configured in a udio e xtract / a udio i nsert m ode with two active hdmi rx inputs and two hdmi tx outputs in use . audio extracted from both hdmi rx inputs and output on ap1_out and ap2_out. audio inserted on hdmi tx outputs from ap1_in and ap2_in input ports , respectively. hbr audio used. 4k 2k at 30 hz video format with pseudo random test pattern applied to both hdmi rx input ports. hdmi rx port termination closed on the two hdmi rx input ports. hdmi tx source termination enab led. osd not enabled. 4 adv7626 configured in s plitter m ode with one hdmi rx input and two hdmi tx outputs in use. 4k 2k at 30 hz video format with pseudo random test pattern applied to one hdm i rx input and output on both hdmi tx outputs using splitter mode. hbr audio from hdmi rx input inserted on the hdmi tx outputs. no audio extraction. hdmi rx port termination closed on the active hdmi rx input port and open on the unused hdmi rx input port . hdmi tx source termination enabled. osd enabled and blended on both hdmi tx outputs using splitter mode. 5 adv7626 configured in power - down mode 0 with two hdmi rx inputs and two hdmi tx output s connected. in p ower - d own m ode 0, all blocks are powered down except for the i 2 c slave. 6 adv7626 configured in power - down mode 1 with two hdmi rx inputs and two hdmi tx outputs connected. in p o wer - d own m ode 1, all blocks are powered down except for the i 2 c slave and the cec (to monitor wake - up interrupts). 7 adv7626 configured in an e xample m aximum o perating m ode with two active hdmi r x inputs and two hdmi tx outputs in use. hbr audio from the two active hdmi rx inputs inserted on the corresponding hdmi tx outputs. no audio extraction. 4k 2k at 30 hz video format with pseudo random test pattern applied to both hdmi rx input ports. hdm i rx port termination closed on the two hdmi rx input ports . hdmi tx source termination enabled. osd not enabled. maximum current consumption values re corded with maximum power supply levels at device maximum operating temperature.
adv7626 data sheet rev. 0 | page 14 of 24 absolute maximum rat ings table 4 . parameter rating avdd_txa to gnd 2.2 v avdd_txb to gnd 2.2 v cvdd to gnd 2.2 v dvdd to gnd 2.2 v pvdd to gnd 2.2 v pvdd_txa to gnd 2.2 v pvdd_txb to gnd 2.2 v dvd dio to gnd 4.0 v tvdd to gnd 4.0 v digital inputs voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v up to a maximum of 4.0 v 5 v tolerant digital inputs to gnd 1 5.5 v digital output s voltage to gnd gnd ? 0.3 v to dvddio + 0.3 v up to a maximum of 4.0 v xt al + , x tal ? pins ?0.3 v to pvdd + 0.3 v maximum junction temperature ( t j max ) 125c storage temperature range ? 65 c to + 150c infrared reflow, soldering (20 sec) 260c 1 the following inputs are 5 v tolerant: ddc_scl_rxa, ddc_sda_rxa, ddc_scl_rxb, ddc _sda_rxb, rxa_5v, rxb_5v, cec_a, ddc_scl_txa, ddc_sda_txa, txa_hpd_arc ? , txa_arc+, cec_b, ddc_scl_txb, ddc_sda_txb, txb_hpd_arc ? , and txb_arc+ . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect de vice reliability. package thermal perf ormance to reduce power consumption when using the adv7626 , the user is advised to turn off unused sections of the device . due to printed circuit board ( pcb ) metal variation and, therefore, variation in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this solut ion eliminates the variance associated with the ja value. do not exceed the maximum junction temperature (t j max ) of 125c. the following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test (dut): t j = t s + ( jt w total ) where: t s is the package surface temperature (c). jt = 0. 41 c/w for the 260- ball csp _ bga (based on 2s2p test board defined in the jedec specification ) . w total = (( pvdd i pvdd ) + ( pvdd_txa i pvdd_txa ) + ( pvdd_txb i pvdd_txb ) + ( tvdd i tvdd ) + ( cvdd i cvdd ) + ( av d d _ t x a i avdd_txa ) + ( avdd_txb i avdd_txb ) + ( dvdd i dvdd ) + ( dvddio i dvddio )) note that this calculation assumes a configuration of two active hdmi rx inputs and t wo active hdmi tx outputs, where termi - nation is open on the unused rx input ports. a configuration of one active hdmi rx input and two active hdmi tx outputs (splitter mode) result s in approximately 112 mw extra power dissipation on chip. esd caution
dat a sheet adv7626 rev. 0 | page 15 of 24 pin configuration an d function descripti ons a gnd rxa_2+ rxa_1+ rxa_0+ rxa_c+ cvdd rxb_2+ rxb_1+ rxb_0+ rxb_c+ cvdd nc nc nc nc cvdd nc gnd b gnd rxa_2? rxa_1? rxa_0? rxa_c? cvdd rxb_2? rxb_1? rxb_0? rxb_c? cvdd nc nc nc nc cvdd nc gnd c gnd cvdd cvdd tvdd tvdd gnd gnd tvdd tvdd gnd gnd tvdd tvdd gnd gnd cvdd gnd gnd d int1 int2 sc l sd a cs rxa_5v rxa_h p a ddc_ scl_rx a ddc_ sda_rx a ddc_ scl_rxb ddc_ sda_rxb rxb_h p a rxb_5v test6 nc tvdd nc nc e ap1_ out0 ap1_ out1 ap1_ out2 ap1_ out3 ap1_ out4 ap1_ out5 ap1_ out_ mclk ap1_ out_ sclk alsb reset nc tvdd nc nc f ap2_ out0 ap2_ out1 nc gnd nc nc g ap2_ out2 ap2_ out3 dvdd dvdd dvdd dvdd dvdd test5 test7 test8 gnd nc nc h ap2_ out4 ap2_ out5 dvddio gnd gnd gnd gnd gnd nc nc gnd cvdd cvdd j ap2_ out_ mclk ap2_ out_ sclk test9 test10 dvddio gnd gnd gnd gnd gnd tvdd nc nc k gnd gnd test 1 1 test12 gnd gnd gnd gnd gnd gnd tvdd nc nc l xt al+ xt al? test13 test14 gnd gnd gnd gnd gnd gnd nc gnd nc nc m pvdd pvdd test3 test2 gnd gnd gnd gnd gnd gnd nc gnd nc nc n gnd gnd pvdd_ tx a pvdd_ tx a gnd gnd cvdd cvdd p txa_c? txa_c+ gnd r_tx a test15 test16 test4 test1 r txa_0? txa_0+ gnd a vdd_ tx a txb_ hpd_ arc? r_txb gnd txb_ arc+ ddc_ sda_txb ddc_ scl_txb cec_b dvddio ep_cs test17 t txa_1? txa_1+ gnd a vdd_ tx a cec_ a gnd gnd gnd gnd a vdd_ txb a vdd_ txb dvddio ep_sclk test18 u txa_2? txa_2+ gnd pvdd_ txb gnd txb_c+ txb_0+ txb_1+ txb_2+ gnd ep_mosi gnd v gnd gnd gnd ddc_ sda_ tx a txa_ hpd_ arc? ddc_ scl_ tx a pvdd_ txb gnd txb_c? txb_0? txb_1? txb_2? gnd ep_miso gnd 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 ap2_in_ sclk ap2_in_ mclk ap1_in_ sclk ap1_in_ mclk ap2_in4 ap2_in2 ap2_in0 ap2_in5 ap2_in3 ap2_in1 ap1_in4 ap1_in2 ap1_in0 ap1_in5 ap1_in3 ap1_in1 txa_ arc+ 1 1832-007 figure 17 . pin configuration table 5 . pin functio n descriptions pin no. mnemonic function description a1 gnd ground ground . a2 rxa_2+ hdmi rx input hdmi rxa channel 2 true input . a3 rxa_1+ hdmi rx input hdmi rxa channel 1 true input . a4 rxa_0+ hdmi rx input hdmi rxa channel 0 true input . a5 rxa_c+ hdmi rx input hdmi rxa clock true input . a6 cvdd power comparator power supply (1.8 v) . a7 rxb_2+ hdmi r x input hdmi rxb channel 2 true input . a8 rxb_1+ hdmi rx input hdmi rxb channel 1 true input . a9 rxb_0+ hdmi rx input hdmi rxb channel 0 true input . a10 rxb_c+ hdmi rx input hdmi rxb clock true input . a11 cvdd power comparator power supply (1.8 v) . a1 2 nc do not connect leave this pin floating .
adv7626 data sheet rev. 0 | page 16 of 24 pin no. mnemonic function description a13 nc do not connect leave this pin floating. a14 nc do not connect leave this pin floating. a15 nc do not connect leave this pin floating. a16 cvdd power comparator power supply (1.8 v) . a17 nc do not con nect leave this pin floating. a18 gnd ground ground . b1 gnd ground ground . b2 rxa_2 ? hdmi rx input hdmi rxa channel 2 complement input . b3 rxa_1 ? hdmi rx input hdmi rxa channel 1 complement input . b4 rxa_0 ? hdmi rx input hdmi rxa channel 0 complement input . b5 rxa_c ? hdmi rx input hdmi rxa clock complement input . b6 cvdd power comparator power supply (1.8 v) . b7 rxb_2 ? hdmi rx input hdmi rxb channel 2 complement input . b8 rxb_1 ? hdmi rx input hdmi rxb channel 1 complement input . b9 rxb_0 ? hdmi rx input hdmi rxb channel 0 complement input . b10 rxb_c ? hdmi rx input hdmi rxb clock complement input . b11 cvdd power comparator power supply (1.8 v) . b12 nc do not connect leave this pin floating. b13 nc do not connect leave this pin floating. b14 nc d o not connect leave this pin floating. b15 nc do not connect leave this pin floating. b16 cvdd power comparator power supply (1.8 v) . b17 nc do not connect leave this pin floating. b18 gnd ground ground . c1 gnd ground ground . c2 cvdd power comparator power supply (1.8 v) . c3 cvdd power comparator power supply (1.8 v) . c4 tvdd power hdmi rx terminator supply voltage (3.3 v) . c5 tvdd power hdmi rx terminator supply voltage (3.3 v) . c6 gnd ground ground . c7 gnd ground ground . c8 tvdd power hdmi rx terminator supply voltage (3.3 v) . c9 tvdd power hdmi rx terminator supply voltage (3.3 v) . c10 gnd ground ground . c11 gnd ground ground . c12 tvdd power hdmi rx terminator supply voltage (3.3 v) . c13 tvdd power hdmi rx terminator supply voltage (3.3 v ) . c14 gnd ground ground . c15 gnd ground ground . c16 cvdd power comparator power supply (1.8 v) . c17 gnd ground ground . c18 gnd ground ground . d1 int1 control interrupt o utput. this pin can be active low or high. when an unmasked status bit changes, an interrupt is generated on this pin . d2 int2 control interrupt o utput . this pin can be active low or high. when an unmasked status bit changes, an interrupt is generated on this pin . d3 scl i 2 c c ontrol i 2 c clock input. this pin is open drain; connect t his pin to a 3.3 v supply using a 4.7 k resistor . d4 sda i 2 c c ontrol i 2 c data input. this pin is open drain; connect this pin to a 3.3 v supply using a 4.7 k resistor . d5 cs digital i nput chip select pin. this pin must be set low or left floating for the chip t o process i 2 c messages that are destined for the adv7626 . the adv7626 ignores i 2 c messages when this pin is high. d6 rxa_5v hdmi rx i nput hdmi rxa 5 v detect pin .
dat a sheet adv7626 rev. 0 | page 17 of 24 pin no. mnemonic function description d7 rxa_hpa hdmi rx output hdmi rxa hot plug assert . d8 ddc_scl_rxa hdmi rx ddc hdcp slave serial clock for hdmi rxa . d9 ddc_sda_rxa hdmi rx ddc hdcp slave serial data for hdmi rxa . d10 ddc_scl_rxb hdmi rx ddc hdcp slave se rial clock for hdmi rxb . d11 ddc_sda_rxb hdmi rx ddc hdcp slave serial data for hdmi rxb . d12 rxb_hpa hdmi rx output hdmi rxb hot plug assert . d13 rxb_5v hdmi rx input hdmi rxb 5 v detect pin . d14 nc do not connect leave this pin floating. d15 test6 t est p in connect this pin to ground using a 4.7 k resistor. d16 tvdd power hdmi rx terminator supply voltage (3.3 v) . d17 nc do not connect leave this pin floating. d18 nc do not connect leave this pin floating. e1 ap1_out0 audio o utput audio output port 1 , output 0 . e2 ap1_out1 audio o utput audio output port 1 , output 1 . e3 alsb i 2 c c ontrol pin to set the i 2 c address of the i/o r egister m ap for the device. when the alsb pin is tied low, the i/o r egister m ap i 2 c address is 0xb0. when the alsb pin is tied high, the i/o r egister m ap i 2 c address is 0x b2. e4 reset miscellaneous d igital reset pin . e15 nc do not connect leave this pin floating. e16 tvdd power hdmi rx terminator supply voltage (3.3 v) . e17 nc do not connect leave this pin floating. e18 nc do not connect leave th is pin floating. f1 ap1_out2 audio o utput audio output port 1 , output 2 . f2 ap1_out3 audio o utput audio output port 1 , output 3 . f3 ap2_out0 audio o utput audio output port 2 , output 0 . f4 ap2_out1 audio o utput audio output port 2 , output 1 . f15 nc do not connect leave this pin floating. f16 gnd ground ground . f17 nc do not connect leave this pin floating. f18 nc do not connect leave this pin floating. g1 ap1_out4 audio o utput audio output port 1 , output 4 . g2 ap1_out5 audio o utput audio output por t 1 , output 5 . g3 ap2_out2 audio o utput audio output port 2 , output 2 . g4 ap2_out3 audio o utput audio output port 2 , output 3 . g7 dvdd power digital power supply (1.8 v) . g8 dvdd power digital power supply (1.8 v) . g9 dvdd power digital power supply ( 1.8 v) . g10 dvdd power digital power supply (1.8 v) . g11 dvdd power digital power supply (1.8 v) . g12 test5 test p in test p in 5 . leave this pin floating. g15 test7 test p in connect this pin to ground using a 4.7 k resistor. g16 gnd ground ground . g17 nc do not connect leave this pin floating. g18 nc do not connect leave this pin floating. h1 ap1_out_mclk audio o utput audio output port 1 , mclk . h2 ap1_out_sclk audio o utput audio output port 1 , sclk . h3 ap2_ou t4 audio o utput audio output port 2 , output 4 . h4 ap2_out5 audio o utput audio output port 2 , output 5 . h7 dvddio power digital interface supply (3.3 v) . h8 gnd ground ground . h9 gnd ground ground . h10 gnd ground ground . h11 gnd ground ground .
adv7626 data sheet rev. 0 | page 18 of 24 pin no. mnemonic function description h12 gn d ground ground . h15 nc do not connect leave this pin floating. h16 gnd ground ground . h17 cvdd power comparator power supply (1.8 v) . h18 cvdd power comparator power supply (1.8 v) . j1 ap2_out_mclk audio o utput audio output port 2 , mclk . j2 ap2_out_ sclk audio o utput audio output port 2 , sclk . j3 test9 test p in connect this pin to ground using a 4.7 k resistor. j4 test10 test p in connect this pin to ground using a 4.7 k resistor. j7 dvddio power digital interface supply (3.3 v) . j8 gnd ground gr ound . j9 gnd ground ground . j10 gnd ground ground . j11 gnd ground ground . j12 gnd ground ground . j15 test8 test p in connect this pin to ground using a 4.7 k resistor. j16 tvdd power hdmi rx terminator supply voltage (3.3 v) . j17 nc do not connect l eave this pin floating. j18 nc do not connect leave this pin floating. k1 gnd ground ground . k2 gnd ground ground . k3 test11 test p in connect this pin to ground using a 4.7 k resistor. k4 test12 test p in connect this pin to ground using a 4.7 k resi stor. k7 gnd ground ground. k8 gnd ground ground. k9 gnd ground ground. k10 gnd ground ground. k11 gnd ground ground. k12 gnd ground ground. k15 nc do not connect leave this pin floating. k16 tvdd power hdmi rx terminator supply voltage (3.3 v) . k 17 nc do not connect leave this pin floating. k18 nc do not connect leave this pin floating. l1 x tal+ miscellaneous d igital adv7626 crystal input . l2 x tal ? miscellaneous d igital adv7626 crystal output . l3 test13 test p in connect this pin to ground using a 4.7 k resistor. l4 test14 test p in connect this pin to ground using a 4.7 k resistor. l7 gnd ground ground . l8 gnd ground ground . l9 gnd ground ground . l10 gnd ground ground . l11 gnd ground ground . l12 gnd ground ground . l15 nc do not connect leave this pin floating. l16 gnd ground ground . l17 nc do not connect leave this pin floating . l18 nc do not connect leave this pin floating. m1 pvdd power pll digital supply (1.8 v) . m2 pvdd power pll digital supply (1.8 v) . m3 test3 test p in test p in 3 . leave this pin floating. m4 test2 test p in test p in 2 . leave this pin floating. m7 gnd ground ground . m8 gnd ground ground .
dat a sheet adv7626 rev. 0 | page 19 of 24 pin no. mnemonic function description m9 gnd ground ground . m10 gnd ground ground . m11 gnd ground ground . m12 gnd ground ground . m15 nc do not connect leave this pin floating. m16 gnd ground ground . m17 nc do not connect leave this pin floating. m1 8 nc do not connect leave this pin floating. n1 gnd ground ground . n2 gnd ground ground . n3 pvdd_txa power hdmi txa pll power supply (1.8 v) . n4 pvdd_txa power hdmi txa pll power supply (1.8 v) . n15 gnd ground ground . n16 gnd ground ground . n17 cvdd power comparator power supply (1.8 v) . n18 cvdd power comparator power supply (1.8 v) . p1 txa_c ? hdmi tx o utput hdmi txa clock complement output . p2 txa_c+ hdmi tx o utput hdmi txa clock true output . p3 gnd ground ground . p4 r_txa hdmi tx in put this p in s ets the i nternal r eference c urrents for hdmi txa. place a 470 resistor (1% tolerance) between this pin and gnd . place t he external resistor as close as possible to the adv7626 . p15 test15 test p in connect this pin to ground using a 4.7 k resistor. p16 test 16 test p in connect this pin to ground using a 4.7 k resistor. p17 test4 test p in test p in 4 . leave this pin floating. p18 test1 test p in test p in 1 . leave this pin floating. r1 txa_ 0 ? hdmi tx o utput hdmi txa channel 0 complement output . r2 txa_0+ hdmi tx o utput hdmi txa channel 0 true output . r3 gnd ground ground . r4 avdd_txa power hdmi txa analog supply (1.8 v) . r5 txb_hpd_arc ? hdmi tx in put hdmi txb hot plug detect (hpd) signal and audio return channel complement input. r6 r_txb hdmi tx in put this pin s ets the i nternal r eference c urrents for hdmi txb. place a 470 resistor (1% tolerance) between this pin and gnd . place t he external resistor as close as possible to the adv7626 . r7 gnd ground ground . r8 txb_arc+ hdmi tx in put hdmi txb audio return channel true input . r9 ddc_sda_txb hdmi tx ddc hdcp slave serial data for hdmi txb . r10 ddc_scl_txb hdmi tx ddc hdcp sla ve serial clock for hdmi txb . r11 cec_b hdmi tx cec hdmi txb consumer electronics control (cec) . r12 dvddio power digital interface supply (3.3 v) . r13 ep_ cs serial p ort c ontrol spi chip select interface for the osd . r14 ap2_in_s clk a udio i nput audio input port 2 , sclk . r15 ap2_in4 a udio i nput audio input port 2 , input 4 . r16 ap2_in2 a udio i nput audio input port 2 , input 2 . r17 ap2_in0 a udio i nput audio input port 2 , input 0 . r18 test17 test p in connect this pin to ground usin g a 4.7 k resistor. t1 txa_1 ? hdmi tx o utput hdmi txa channel 1 complement output . t2 txa_1+ hdmi tx o utput hdmi txa channel 1 true output . t3 gnd ground ground . t4 avdd_txa power hdmi txa analog supply (1.8 v) . t5 cec_a hdmi tx cec hdmi txa consumer electron ics control (cec) . t6 gnd ground ground . t7 gnd ground ground .
adv7626 data sheet rev. 0 | page 20 of 24 pin no. mnemonic function description t8 gnd ground ground . t9 gnd ground ground . t10 avdd_txb power hdmi txb analog supply (1.8 v) . t11 avdd_txb power hdmi txb analog supply (1.8 v) . t12 dvddio power digital interface suppl y (3.3 v) . t13 ep_sclk serial p ort c ontrol spi clock interface for the osd . t14 ap2_in_mclk a udio i nput audio input port 2 , mclk . t15 ap2_in5 a udio i nput audio input port 2 , input 5 . t16 ap2_in3 a udio i nput audio input port 2 , input 3 . t17 ap2_in1 a ud io i nput audio input port 2 , input 1 . t18 test18 test p in connect this pin to ground using a 4.7 k resistor. u1 txa_2 ? hdmi tx o utput hdmi txa channel 2 complement output . u2 txa_2+ hdmi tx o utput hdmi txa channel 2 true output . u3 gnd ground ground . u4 ddc_scl_txa hdmi tx ddc hdcp slave serial clock for hdmi txa . u5 txa_arc+ hdmi tx in put hdmi txa audio return channel true input . u6 pvdd_txb power hdmi txb pll power supply (1.8 v) . u7 gnd ground ground . u8 txb_c+ hdmi tx o utput hdmi txb clock tru e output . u9 txb_0+ hdmi tx o utput hdmi txb channel 0 true output . u10 txb_1+ hdmi tx o utput hdmi txb channel 1 true output . u11 txb_2+ hdmi tx o utput hdmi txb channel 2 true output . u12 gnd ground ground . u13 ep_mosi serial p ort c ontrol spi master ou t put /slave in put for osd . u14 ap1_in_sclk a udio i nput audio input port 1 , sclk . u15 ap1_in4 a udio i nput audio input port 1 , input 4 . u16 ap1_in2 a udio i nput audio input port 1 , input 2 . u17 ap1_in0 a udio i nput audio input port 1 , input 0 . u18 gnd grou nd ground . v1 gnd ground ground . v2 gnd ground ground . v3 gnd ground ground . v4 ddc_sda_txa hdmi tx ddc hdcp slave serial data for hdmi txa . v5 txa_hpd_arc ? hdmi tx in put hdmi txa hot plug detect (hpd) signal and audio return channel complement input. v6 pvdd_txb power hdmi txb pll power supply (1.8 v) . v7 gnd ground ground . v8 txb_c ? hdmi tx o utput hdmi txb clock complement output . v9 txb_0 ? hdmi tx o ut put hdmi txb channel 0 complement output . v10 txb_1 ? hdmi tx o utput hdmi txb channel 1 complement output . v11 txb_2 ? hdmi tx o utput hdmi txb channel 2 complement output . v12 gnd ground ground . v13 ep_miso serial p ort c ontrol spi master in put /slave out p ut for osd . v14 ap1_in_mclk a udio i nput audio input port 1 , mclk . v15 ap1_in5 a udio i nput audio input port 1 , input 5 . v16 ap1_in3 a udio i nput audio input port 1 , input 3 . v17 ap1_in1 a udio i nput audio input port 1 , input 1 . v18 gnd ground ground .
dat a sheet adv7626 rev. 0 | page 21 of 24 p ower s upply recommendation s power - up sequence the power - up sequence for the adv7626 is as follows : 1. hold the reset pin low. 2. power up the 3.3 v supplies (dvddio and tvdd). 3. after the 3.3 v supplies reach their minimum recom - mended value of 3.14 v , wait at least 20 ms before powering up the 1.8 v supplies. 4. power up the 1.8 v supplies (avdd_txa, avdd_txb, cvdd, dvdd, pvdd, pvdd_txa, and pvdd_txb). these supplies s hould be powered up at the same time; that is, there should be a difference of less than 0.3 v between them. 5. release the reset pin after all supplies are established . a fter power - up , a complete reset is recommended . this reset can be performed by the syste m microcontroller. t pss 20ms r e s e t > 5 m s reset 1 . 8 v s u p p l y 3 . 3 v s u p p l y 0 v 0 v 0 v 3 . 3 v 3 . 3 v 1 . 8 v 3 . 1 4 v 1 1832-022 figure 18 . adv7626 supply power - up sequence power - down sequence the adv7626 supplies can be de asserted simultaneously as long as dvddio or tvdd does not fall below a lower rated supply.
adv7626 data sheet rev. 0 | page 22 of 24 theory of operation hdmi receiver the adv7626 front end incorporates two hdmi receivers capab le of receiving all hdtv formats up to 3 ghz (4k 2k at 24 hz/25 hz/30 hz) . the hdmi receivers also support hdmi features including 3d tv and content type bits. each hdmi receiver in the adv7626 incorporates an adaptive equalizer , which compensates for the high frequency losses inherent in hdmi and dvi cabling, especially at longer lengths and higher frequencies. the adv7626 features a 768 - byte internal edid memory space , which can be used to store two independent edids , one for each receiv er . the memory can be partitioned to provide two 256 - byte edids or one 512 - byte extended edid and one 256 - byte edid. either edid can be replicat ed on any input port . the two hdmi receivers offer advanced audio functionality. each receiver supports multichannel i 2 s audio for up to eight channels. the receivers also support a six - dsd channel interface, with each channel carrying an oversampled 1 - bit repre sentation of the audio signal as delivered on sacd. the adv7626 can also receive hbr audio packet streams and output them through the hbr interface in an s/pdif format that conforms to the iec 60 958 standard. s/pdif is supported via the hpd back channel. the receivers also contain an audio mute controller that can detect a variety of conditions that can result in audible extraneous noise in the audio output. on detection of these conditions, the a udio data can be ramped to prevent audio clicks or pops. hdcp repeater functionali ty with the inclusion of hdcp 1.4, displays can receive encrypted video content. the hdmi interface of the adv7626 allows authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during trans - mission , as specified by the hdcp 1.4 protocol. repeater support is also offered by the adv7626 . digital audio ports the adv7626 features two independent audio input ports and two independent audio output ports . the audio input and output ports pro vide comprehensive muxing support for the destination of the audio ( for example, to either hdmi transmitter or either audio output port) and support for the source of the audio ( for example, from either hdmi receiver or from either audio input port). the e xtracted audi o can be processed by a sharc? p ro- cessor and can be reinserted back into the hdmi output stream or output via the hardware connected to the system. on - screen display a key feature of the adv7626 is the on - chip character - and icon - based osd generator. the generated osd can be converted to match the 4:2:2 or 4:4:4 input format in either the rgb or ycrcb color spaces. after the osd is generated, it is overlaid at the output resolution (any video resolution up to 4k 2k at 24 hz/25 hz/30 hz ) for best performance. the osd portion of the image is optionally semitransparent using a 5 - bit alpha blend betwe en the input video and the osd. the osd font characters and icons can be stored in ex ternal spi flash memory , read directly into ram, or they can be loaded in to the on - chip ram via the spi or i 2 c interface . hdmi transmitter s the adv7626 incorporates dual hdmi transmitters , support ing all hdtv formats up to 3 ghz (4k 2k at 24 hz/25 hz/30 hz ) , arc , and all mandatory 3d tv formats. the hdmi transmitter can output any audio mode received from the hdmi receiver , including au dio sample packets, hbr , or dsd. the arc receiver s upp ort s both single - ended and differential modes and simplifies cabling by combining an upstream audio capability in a conventional hdmi cable. each transmitter features an on - chip mpu with an i 2 c master to perform hdcp operations and edid read operations. i 2 c interface the adv7626 supports a 2 - wire serial (i 2 c - compatible) micro processor bus driving multiple peripherals. the adv7626 is cont rolled by an external i 2 c master devi ce, such as a micro - controller. other features other features of t he adv7626 include the following: ? fully qualified software low level libraries, driver, and application ? complete input and output audio support ? programmable interrupt request output pins: int1 and int2 ? chip select and alsb ? low power consumption: 1.8 v digital core, 1.8 v analog, and 3.3 v digital input/output ? temperature range: 0c to 70c ? 15 mm 15 mm, pb - free, 260- ball csp_ bga
dat a sheet adv7626 rev. 0 | page 23 of 24 outline dimensions a b c d e f g 9 8 11 10 13 12 7 6 5 4 2 3 1 13.60 bsc sq h j k l m n p r t u v 0.35 nom 0.30 min 15.10 15.00 sq 14.90 1.50 1.36 1.21 1.11 1.01 0.91 15 14 17 16 18 compliant to jedec standards mo-275-kkab-1. 1 1-18-2013-b 0.50 0.45 0.40 coplanarit y 0.20 ball diameter 0.80 bsc de t ai l a a1 ball corner a1 ball corner detail a bottom view top view seating plane figure 19 . 260 - ball chip scale package ball grid array [csp_bga] (bc - 260 - 1) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package descriptio n package option adv762 6 kbcz -8 0c to 70c 260- ball chip scale package ball grid array [csp _ bga] bc -260-1 adv762 6 kbcz -8 -rl 0c to 70c 260- ball chip scale package ball grid array [csp _ bga] bc -260-1 eval - adv7625 -sm z evaluation board 1 z = rohs compliant part. 2 this part is programmed with internal hdcp keys. customers must have hdcp adopter status (consult digital content protection, llc, for licensing requirements) to purchase any components with internal hdcp keys.
adv7626 data sheet rev. 0 | page 24 of 24 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors) . hdmi, the hdmi logo, and high - definition multimedia interface are trademarks or registered trademarks of hdmi licensin g llc in the united states and other countries. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11832 - 0 - 12/13(0)

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